The present invention generally relates to fabrication of semiconductor devices including integrated circuits and more particularly to a fabrication process of a semiconductor device having a multilayer interconnection structure.
Semiconductor integrated circuits generally have a multilayer interconnection structure. In a multilayer interconnection structure, a conductive region formed in a substrate or a lower conductor pattern forming a part of the multilayer interconnection structure, is connected to an upper conductor pattern via a contact hole formed in an intervening interlayer insulation film, wherein the upper conductor pattern and the interlayer insulation film form the multilayer interconnection structure together with the lower interconnection pattern and the contact hole.
With increasing miniaturization of semiconductor devices and associated increase of the integration density of semiconductor integrated circuits, in which such miniaturized semiconductor devices are included, there emerges a difficulty in achieving a reliable electrical interconnection by way of a conventional sputtering process of Al alloys. More specifically, the Al-alloy layer formed as a result of such a sputtering process tends to show a poor step coverage when filling miniaturized contact holes that have a large aspect ratio.
In order to overcome the problem of poor reliability of electrical contact in such a miniaturized multilayer interconnection structure, it is practiced to fill the contact hole by a conductive material by a vapor phase deposition process and provide the upper interconnection pattern in contact with such a conductive material filling the contact hole. By using such a vapor phase deposition process, it is possible to deposit a conductive material inside a deep contact hole in conformity with the shape thereof even when the contact hole has a large aspect ratio. On the other hand, the conductive material that can be deposited by such a vapor phase deposition process is limited. Typically, W is used for this purpose.
FIG. 1 shows the structure of such a conventional multilayer interconnection structure.
Referring to FIG. 1, the multilayer interconnection structure is formed on a substrate or a semiconductor layer 41 that carries an insulation layer 42 typically an oxide layer thereon, and includes a lower conductor pattern 43 covered by an interlayer insulation film 30. The interlayer insulation film 30 is formed with a contact hole 30A exposing a part of the lower conductor pattern 43, and the contact hole 30 is filled by a conductive plug 32 typically of W. Further, an upper conductor pattern 37 typically of an Al alloy is formed on the insulation film 30 in contact with the conductive plug 32. In the example of FIG. 1, an adhesion layer 31 of a Ti alloy or TiN is provided between the insulation film 30 and the interconnection pattern 37.
In such a structure, it is generally possible to fill the contact hole 30A without encountering the problem of poor step coverage, by using a vapor phase deposition process for the formation of the conductive plug 32.
In the contact structure of FIG. 1, however, there still arises a problem of poor step coverage associated with the incomplete filling of the contact hole 30A by the W plug 32. In FIG. 1, it will be noted that the W plug 32 fills only a part of the contact hole 30A. Because of this, it is necessary that the Al-alloy pattern 37 fills the upper part of the contact hole 30A, while filling of the contact hole 30A having such a large aspect ratio by a sputtering process is still difficult, although the degree of difficulty is reduced as compared with the case of filling the entire contact hole 30A.
FIG. 2 shows the cross section of a contact hole having an aspect ratio of 1 by an Al-alloy layer deposited by a sputtering process, wherein it will be noted that the opening at the top edge of the contact hole becomes smaller with increasing thickness of the Al-alloy layer deposited on the insulation layer. On the other hand, no substantial growth occurs for the Al-alloy layer covering the bottom part, particularly the side wall of the contact hole. In the example of FIG. 3, it should be noted that the contact hole is defined by a vertical side wall.
The reason why filling of the contact hole by the W plug 32 becomes incomplete in the structure of FIG. 1 will now be explained.
Referring to FIG. 3A showing the process of forming such a plug 32, a W layer 32' is deposited on the interlayer insulation film 30 covered by the adherence film 31. In such a multilayer interconnection structure, it should be noted that there generally exist an irregularity on the top surface of the interlayer insulation film 30, reflecting a structure underlying the insulation film 30. In other words, the top surface of the insulation film 30 is not completely flat but there may be a depression 33 of which depth may reach as much as several hundred nanometers.
Next, in the step of FIG. 3B, the W layer 32' is subjected to an etch-back process, wherein the etch-back process is continued until the adhesion layer 31 on the top surface of the interlayer insulation film 30 is exposed as indicated in FIG. 3C. Thereby, the W plug 32 is obtained in the contact hole 30A.
In the state of FIG. 3C, it should be noted that, while the W layer 32' is removed from the majority of the top surface of the interlayer insulation film 30, the W layer 32' does remain in the foregoing depression 33 to form a W pattern 34 therein. As such a W pattern 34 may cause an unwanted short-circuit, it has been necessary to continue the etch-back process, until the W pattern 34 is removed completely from the entire surface of the layer 30. However, such an excessive etch-back process inevitably causes an excessive etch-back also in the W plug 32 filling the contact hole 30A. Thereby, an unfilled space 35 is formed inevitably on the top part of the plug 32.
It will be noted that the more the undulation of the interlayer insulation film 30, the more the proportion of the unfilled space 35 in the contact hole 30A. Thus, the foregoing problem of poor step coverage of the upper conductor pattern 37 appears conspicuous particularly in the multilayer interconnection structure including two or more interlayer insulation layers.
In order to overcome the foregoing problem, the Japanese Laid-open Patent Publication 5-121564 describes a process to etch-back the interlayer insulation film 30 subsequently to the step of FIG. 3D, such that the interlayer insulation film 30 has a flush surface with the conductor plug 32. However, such an etching of the insulation film uniformly over a wide area is difficult to achieve due to the problem of local fluctuation of the etching rate, and there is a tendency that severe irregularity appears on the top surface of the interlayer insulation film 30 as a result of such an etching. Further, such a conventional process requires formation of a deep contact hole in the insulation film before it is etched to the desired thickness, while exposure of such a deep contact hole is substantially difficult when a high resolution exposure system is used. In conclusion, the process of the foregoing prior art is difficult to implement in the real production process of semiconductor devices and integrated circuits.
It is of course possible to planarize the structure of FIG. 3D by a chemical mechanical polishing (CMP) process. In such a case, the depression 33 is eliminated successfully together with the residual W pattern 34, and the problem of incomplete filling of the contact hole 30A by the W plug 32 is avoided. However, such a CMP process has to be conducted outside the deposition chamber in which the deposition is conducted, and the deposition process conducted therein for forming the multilayer interconnection structure is inevitably interrupted. As a consequence, the throughput of fabrication of the semiconductor integrated circuit is deteriorated.